`include "defines.v"

module CSR (
    input  wire         clk,
    input  wire         rst,

    //read port
    input  wire         csr_ena,
    input  wire [11: 0] csr_addr,
    output wire [`xlen] csr_data,

    //write port
    input  wire         csr_wen,
    input  wire [11: 0] csr_waddr,
    input  wire [`xlen] csr_wdata
);
    
reg [`xlen] mcycle;

always @(posedge clk) begin
    if(rst) mcycle <= `ZERO_WORD;
    else if(csr_wen & csr_waddr == 12'hB00) mcycle <= csr_wdata;
    else mcycle <= mcycle + 64'b1;
end

assign csr_data = (rst | ~csr_ena) ? `ZERO_WORD : (csr_addr == 12'hB00) ? mcycle : 64'b0;

endmodule